1. Field of the Invention
The present invention generally relates to transistor devices, and more particularly, the present invention relates to devices having transistors containing respectively different high-k gate dielectrics, and to processes for forming such devices.
2. Description of the Related Art
Conventional transistor devices, such as metal-oxide-semiconductor (MOS) devices, are characterized by a gate dielectric of silicon dioxide (SiO2) interposed between a gate electrode and a channel region. The performance of such devices can be improved by increasing the capacitance between the gate electrode and channel region, and one common method by which the capacitance has been increased is to decrease the thickness of the SiO2 gate dielectric below 100 angstroms. In fact, the thickness of the gate dielectric is currently approaching 40 angstroms. Unfortunately, however, at around this thickness, the use of SiO2 as a gate dielectric becomes limited. This is because direct tunneling through the SiO2 dielectric to the channel region can occur in the case where the SiO2 dielectric is less than about 40 angstroms. The result is increased leakage current and increased power consumption.
Accordingly, methods have been sought to reduce leakage current while achieving a high gate capacitance. One method investigated by the industry is the use of materials having a high dielectric constant (high-k or high-∈) for the gate dielectric layer. Generally, gate capacitance (C) is proportional to permitivity (∈) and inversely proportional to thickness (t) (i.e., C=∈A/t, where A is a constant). Thus, an increase in thickness (t) (e.g., to 40 angstroms or more) for reducing leakage current can be offset by the high permitivity (∈).
However, the use of high-k dielectrics for gate dielectric layers suffers drawbacks when used in MOS devices containing both PMOS and NMOS transistors. This is at least partly because high dielectric materials contain a greater number of bulk traps and interface traps than thermally grown SiO2. These traps adversely affect the threshold voltage (Vt) characteristics of the PMOS and NMOS devices. Therefore, the industry has been seeking a solution to enable fabrication of reliable high-k gate dielectric layers while minimizing the number of bulk and interface traps.